מציאת משרת הייטק בחברות הטובות ביותר מעולם לא הייתה קלה יותר
What you’ll be doing:
Responsible for verifying the ASIC design, architecture and micro-architecture using advanced verification methodologies.
Expected to understand the design and implementation, define the verification scope, develop the verification infrastructure and verify the correctness of the design.
Come up with test plans, tests and verification infrastructure for complex IPs/sub-systems.
Responsible for performance and deadlock verification of the GPU memory subsystem unit.
Build reusable bus functional models, monitors, checkers and scoreboards following coverage driven verification methodology.
Perform functional coverage driven verification closure.
Working with architects, designers, and pre and post silicon verification teams to accomplish your tasks.
What we need to see:
B.Tech./ M.Tech. with 6+ years of relevant experience
Experience in verification of complex IPs/units and sub-systems
Verification experience using random stimulus along with functional coverage and assertion-based verification methodologies
Expertise in Verilog
Knowledge in SystemVerilog or similar HVL
Familiarity with verification methodologies like UVM/VMM and exposure to industry standard verification tools for simulation and debug
Ways to stand out from the crowd:
Experience in memory subsystem or network interconnect IP verification
Good debugging and analytical skills
Scripting knowledge (Python/Perl/shell)
Good communication skills & dream to work as a great teammate
משרות נוספות שיכולות לעניין אותך