Microsoft Senior Analog Design Engineer 

India, Karnataka, Bengaluru 

864206729

• You should have a BSEE or equivalent, MSEE/PhD preferred.
• You should have at least 10-15 years of Analog & Mixed Signal IC circuit design delivery of medium-large complexity designs.
• You have delivered Analog IP’s successfully in mass production in FinFET processes.
• You have a proven track record at each of the following stages in product development:
  • Experience in leading high-speed and low-power RX/TX/Clocking designs, High-Speed SerDes or D2D interconnect designs, or large blocks such as PLLs, Power Regulators, Data Converters, etc.
  • Design partitioning, power/jitter budgeting and timing analysis. Knowledge of lower power design techniques, calibration, parasitic extraction, EM/IR/ESD & Signal Integrity Design.
  • Detailed design and mixed signal simulatiins of analog/mixed signal building blocks and one or more of the following subsystems: ADC, DAC, PLL, clocking systems, sampler, RX front-end, TX driver, serializer, de-serializer, voltage regulator, bandgap, bias circuits.
• You have detailed knowledge of EDA tools for Cadence, Mentor, Synopsys for Analog Design.
• You are a self-starter with the ability to define and adhere to a schedule.
• You have good inter-personal skills, you are able to interface with a variety of external partners (customers, architects, designers, project managers, etc.) and are able to deliver complete layouts to customers.

Ability to meet Microsoft, customer and/or government security screening requirementsmay befor this role. These requirementsto pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.

• The primary responsibility of this position is to lead Analog designs and delivery of cutting edge, high-performance, high-speed, low-power Analog IP designs for interconnectivity solutions and fundamental Analog circuit blocks for various Microsoft products in various process nodes including deep FinFet, following industry best practices. You will technically deliver complex blocks that will produce schematics, verify in simulation, and work with mask layout teams to deliver a final IP GDS.
• You will coordinate tasks with junior members of the team, develop plans for Analog IP execution, follow processes/methodologies to deliver IP blocks. You are a very hands-on contributor.
• You are proficient in Analog and Mixed signal IC circuit designs, design validation simulations (pre and post-layout), follow checklists/presentation templates, supervise floor-planning and monitor layout progress. You will coordinate bench validation of IP in Silicon, and IP characterization on bench and tester. You will use established flows/methodologies/processes for execution.
• You will work along with other members of the team to deliver IP’s, including project planning, schedule tracking, report generation.