Nvidia Senior Silicon Product Architect 

United States, Texas 

861630409

What you'll be doing:

• Drive product performance and power targets, trade-offfeatures/configurations,and provide innovative solutions to complex silicon and system-level problems.

• Evaluate market segments and use cases; translate market requirements to engineering problem statements and metrics.

• Innovate Performance, power, yield, and quality optimizations and features for the world’s fastest power-shipping products in the GPU and SoC market segments spanning gaming, automotive, datacenter, and DL/AI.

• Analyze by first principles and influence requirements for multi-functional teams to drive product features to production. Incorporate productization feedback to improve the next generation.

• Lead the team for feature requirements and schedule from architecture to silicon phase of projects.

• Work alongside architects, marketing teams, chip and board designers, software/firmware engineers, HW/SW applications engineering, process/reliability authorities, ATE engineers, and silicon operations in a fast-paced, high-energy, collaborative work environment to bring industry-defining products to market.

• BS or MS in EE, CE, CS, Systems Engineering, or equivalent experience.

• Proven experience of 10+ years in product performance and power evaluations.

• Experience with system-level features, product binning methods, optimization techniques, methods, and data analysis and statistics tools.

• Experience working on new product introduction market analysis. A background in gaming, automotive, and datacenter market segments is helpful.

• Deep understanding of critical path analysis, power/performance analysis, process technologies, and transistor/device physics.

• Familiarity with silicon bring-up and validation, frequency and power characterization, product analysis and optimization; hands-on post-silicon experience is a plus.

• Excellent problem-solving, partnership, and interpersonal skills.

• Experience working with offshore teams is required.

• Exposure to CPU/GPU/SoC architecture and HW-SW co-design is a plus.