Amazon Sr CAD Engineer ASIC 

United States, California, San Diego 

858585027

Project Kuiper is an initiative to launch a constellation of Low Earth Orbit satellites that will provide low-latency, high-speed broadband connectivity.The Role:
As Senior CAD Engineer you will be responsible for installing and maintaining EDA tools and flows for project Kuiper's digital design teams. This is an opportunity to define the digital design environment and deploy methodology of a new project from day one. You will advise on tools selection, and interface with various EDA vendors and foundries to optimize the EDA flows, design collateral, and other files necessary for the design team to operate efficiently. You will be responsible for defining and creating the common design environment that sets the versions of the tools, flows, design IPs, other collateral for every chip in development. Additionally, you will interface various digital design teams who will be requesting deployment, training, and maintenance of tools and flows, and collaborate EDA vendors as needed. In this role you will interface internal stakeholders as well as 3rd party, tracking necessary updates, deploying enhancements following regression sign off.Export Control Requirement:
Key job responsibilities- Develop, regress, and deploy digital front end flows including RTL static checks and design verification methodology
- Develop, regress and deploy digital implementation flows including Synthesis and Formal Verification- Develop standardized CAD flows that can be leveraged across development based on various process technologies in parallel
- Be able to independently troubleshoot digital tool flow usage and deploy solutions
- Fluent in scripting languages such as TCL, Python, etc. and able to build scalable and efficient flows to support parallel design developments
- Understand and leverage nuances of process technologies to optimize design PPA

- Bachelor’s degree in Electrical/Computer Engineering
- 7+ years of silicon digital EDA flow development and/or digital design experience
- Familiar with digital RTL code checks and implementation, including Lint, CDC, RDC, SDC
- Familiar with digital design verification methodology and debugging techniques
- Familiar with basic Synthesis and Formal Verification methodology and flow development experience

- Master’s degree in Electrical/Computer Engineering
- 7+ years of full stack RTL to GDS methodology deployment experience
- Digital design experience with Synthesis and back end hand off ownership
- Digital design RTL2GDS experience with emphasis on methodology and best practice
- Power estimation and optimization
- Back end tool experiences a plus, including Fusion Compiler, PrimeTime, or equivalent
- Strong written and verbal communication skills