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Marvell Senior Distinguished Engineer United States, California 851529676
Today
As a key CAD member of Marvell Central Engineering, you will lead in developing next-generation automated design flow and add-on tools. You will be able to use your extensive design and CAD knowledge to define the organization's design methodology and workflow.
What You Can Expect
The engineer will implement tool flows, develop and define CAD methodologies, and generate scripts. He or she will evaluate tools and be responsible for place and route, timing closure, and backend activities. The engineer will code in scripting languages such as TCL and Unix shell languages (coding in languages such as Python is also possible). The engineer will be required to perform the following ASIC design tasks:
- Block-level layout implementation and timing closure.
- Static Timing and Crosstalk analysis and timing closure.
- Design For Testing analysis and timing closure.
- Synthesis and Physical synthesis.
- Learn design rules of advanced technology nodes.
- Optimize design implementation in terms of timing, area, and power.
- Write thorough documentation.
- Present and defend your decisions and results to the team.
Appropriate training for all required skills will be provided.
What We're Looking For
- The candidate must be pursuing a degree in Electronic Engineering or a related technical field(s).
- Have less than 4 final exams remaining (+ degree thesis ongoing) or less than six months left to finish the career.
- Must be very thorough and detail-oriented.
- Experience in circuit design using CAD tools (Synopsys, Cadence, Mentor) is valuable.
- Fluency in English, both speaking and writing.
- Good Spanish communication skills (verbal and written).
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