Palo Alto Sr Principal ASIC Design Engineer NetSec 

United States, California 

838223442

Being the cybersecurity partner of choice, protecting our digital way of life.

Your Career

Join our ASIC team and help deliver the digital logic that powers our next-generation firewall platforms. As a Senior Principal Engineer, you will take end-to-end ownership of complex modules or subsystems from architectural definition through silicon bring-up. You will provide technical leadership, collaborate extensively with world-class verification and physical design engineers to hit aggressive performance, power, and schedule goals, and mentor less experienced team members. This role requires a deep technical background in ASIC design for networking applications and the ability to independently drive major design efforts.

Your Impact

• Define and document clear, comprehensive design and micro-architecture specifications for complex digital logic blocks and subsystems.

• Design high-quality, high-performance SystemVerilog RTL that meets aggressive area, performance, and power targets, with particular emphasis on complex datapath designs.

• Lead debug efforts across simulation, emulation, formal methods, and silicon bring-up environments.

• Partner closely with verification engineers to define test plans, debug complex scenarios, close coverage, and add design-for-debug features.

• Collaborate effectively with physical design teams, including reviewing synthesis/timing reports, rewriting RTL to close critical paths, analyzing timing, power, and area reports, and consulting on floor-planning for congestion/routability. Drive timing closure from an RTL perspective, understanding core concepts like setup/hold constraints and delay sources.

• Mentor junior and senior staff engineers, providing technical guidance and fostering their growth in ASIC design best practices, particularly in areas like design methodology and problem-solving approach.

Required Qualifications

• BS in EE, CE, or CS (MSEE or equivalent military experience preferred).

• 15+ years of hands-on front-end ASIC design experience, with significant ownership of multiple complex modules or subsystems from specification through mass production silicon.

• Expert-level proficiency in SystemVerilog RTL design.

• Deep and demonstrable strength in digital logic design fundamentals, including state machines, synchronous and asynchronous FIFO design, flow control mechanisms (e.g., ready/valid, credits, backpressure), and the understanding and avoidance of head-of-line blocking and deadlock situations in complex datapaths.

• Expertise in defining micro-architecture from high-level requirements for large and intricate digital blocks.

• Advanced debugging skills across various verification platforms and silicon.

• Strong command of timing, power, and area analysis, with proven ability to analyze reports, identify critical paths, and drive RTL changes to meet targets effectively.

• Proficiency in scripting (Python, C/C++, Perl, bash, or tcsh) for automation and analysis.

• Excellent technical leadership, collaboration, and written/verbal communication skills, including the ability to clearly explain complex design concepts and methodologies.

• Strong networking or cybersecurity domain knowledge.

• Extensive experience with relevant protocols/technologies (e.g., PCIe, Ethernet IEEE 802.3, search-algorithm accelerators, ARM AMBA buses like AXI/AHB/APB, cryptographic algorithms).

• Hands-on silicon validation and lab bring-up experience .

Preferred / Nice-to-Have

• Formal verification ownership and expertise.

• Experience with innovation or piloting new design or verification flows (e.g., AI-driven techniques).

Compensation Disclosure

The compensation offered for this position will depend on qualifications, experience, and work location. For candidates who receive an offer at the posted level, the starting base salary (for non-sales roles) or base salary + commission target (for sales/commissioned roles) is expected to be between $220000 - $252000/YR. The offered compensation may also include restricted stock units and a bonus. A description of our employee benefits may be found .

All your information will be kept confidential according to EEO guidelines.