Microsoft Principal Design Verification Engineer 

India, Karnataka, Bengaluru 

82696789

• 15 or more years of experience in design verification with a proven track record of delivering complex CPU or SoC IP’s
• Experience with verification for multiple product cycles from definition to silicon, including writing test plans, developing tests, debugging failures and coverage signoff in UVM or C++
• Substantial background in debugging RTL (Verilog) designs as well as simulation and/or emulation environments
• Scripting language such as Python or Perl

Desirable:

• Hands on experience in Formal property verification
• knowledge in high-speed protocols like DDR/HBM, PCIe, Ethernet
• Experience of working on AI/ML SoCs

The AISiE silicon team is seeking a passionate, driven, and intellectually curious computer/electrical engineer to deliver premium-quality designs once considered impossible. We are responsible for delivering cutting-edge, custom IP and SoC designs that can perform complex and high-performance functions in an extremely efficient manner.

• Own or lead verification of complex flows at the SOC, subsystem, or IP levels
• Plan the verification of complex design IP/SoC interacting with the architecture and design engineers to identify verification test scenarios.
• Learn about the design and interact with partner teams to define verification strategies and test plans
• Develop verification environments and run and debug simulations to drive quality
• Apply random-stimulus and coverage-based techniques to find bugs and meet test plan goals
• innovate to improve verification efficiency through methodologies or tools
• Coach and mentor others in your areas of expertise
• Demonstrate Microsoft core values: Customer Focus, Adaptability, Collaboration, Growth Mindset, Drive for Results, Influence for Impact, Judgement, and Diversity & Inclusion