ARM Commercial Product Operations Lead 

United States, California, San Jose 

822880428

As part of the methodology team, you will lead the development, improvement, and deployment of low power structural check methodologies across multiple SoC and IP projects. This role involves designing automated flows for UPF/CPF consistency, power domain integrity, and structural rule validation at both RTL and netlist levels. You will collaborate closely with design, verification, and EDA partners to ensure robust, scalable, and high-coverage power-aware design signoff strategies across technology nodes and product segments.

• Develop and maintain low-power structural check methodologies (UPF/CPF validation, isolation, level shifters, retention, domain crossings).
• Build automated flows using tools like Synopsys VC LP, SpyGlass-LP, and Conformal LP.
• Ensure power intent consistency and early issue detection through collaboration with design and verification teams.
• Integrate structural checks into signoff regressions with high coverage and low false positives.
• Work with vendors and internal teams to enhance tools, debug issues, and improve efficiency.
• Drive global adoption through documentation, training, and support.
• Assist in audits, quality reviews, and milestone checks.

• 5+ years of Strong background in low-power structural methodologies and UPF/CPF-based flows.
• Deep understanding of power intent specs, domain partitioning, isolation, and retention.
• Hands-on experience with tools like VC LP, SpyGlass-LP, or Cadence CLP.
• Skilled in scripting (Python, Perl, TCL) for flow automation.
• Experience with large SoC/IP designs across advanced nodes.
• Confirmed ability to debug structural issues and drive closure.
• Strong communication and documentation skills.

• Experience with formal verification or functional simulation for power-aware designs.
• Knowledge of complex power analysis and correlation with structural checks.
• Exposure to hierarchical low-power signoff strategies in multi-voltage or multi-power domain SoCs.
• Familiarity with power-aware DFT, scan strategies, and low-power aware synthesis flows.
• Participation in industry working groups (e.g., Accellera UPF), technical conferences, or publications.
• Involvement in tool benchmarking, vendor collaborations, and internal tool qualification projects.

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