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Intel Global Yield Thin Film Metro Engineer Ireland 815493314
This job is to seek for Thin Film Metro Development engineering roles in FSM HVM Global Yield organization.
Selected candidates will :
Work with other members in metro team, other teams in Global Yield org, fab module, yield, integration, and TD team members to achieve yield ramp-up and yield improving in early production stage, supporting internal and external customers.
Collaborate with Technology Development team and Process Integration team to import and setup new technology to production fabs across the globe.
Identify critical yield limiting parametric steps to set production line monitoring strategy to increase yield and quality with maximum productivity and lowest cost.
Candidate should possess the following
behavioral skills:
Problem-solving and project/program management experience with strong self-initiative and self-learning capabilities.
Demonstrated interpersonal skills to perform at leadership role including influencing, engaging, and motivating.
Proven track record of working across organization through matrix structures to accomplish strategic objectives with conflicting priorities.
Must demonstrate strong communication skills.
Minimum Qualifications:
Bachelor's degree in science and engineering major, with at least 5 - 8 years of experience.
Strong understanding on Thin Film Metro and yield impact in semiconductor high-volume production and proven quantified track record of yield improvement.
8+ years of experience in advanced node semiconductor industry in Thin Film metro or process engineering.
Basic understanding and collaboration experience with processes including lithography, dry etch, wet etch, CMP, diffusion, implant, thin films and metrology.
In addition :
Experience in Statistics and Machine Learning
Experience in working with Process Integration, Design and OPC teams to identify layout-sensitive defect weak points and address systematic defect issues
Knowledge of module tool impacts to defects, inline parametric and yield through PM life while understanding upstream and downstream impacts to other tools
Working knowledge in module processes including lithography, dry etch, wet etch, CMP, diffusion, implant, thin films, and metrology.
Skills to develop improvement projects at module level to improve process for reduced defectivity and improved yield.
Preferred Qualifications:
Experience in FinFET technology development or high-volume manufacturing with hands-on knowledge of FinFET technology process flow to analyze systematic defect sources and set mitigation actions.
Strong data analysis and programming skills - AI/Machine learning, Programming (SQL/Python/MATLAB), Software Development, Data Visualization.
Set up and optimize wafer inspection steps and recipes, to ensure detection of yield detracting defects in line at step.
Experience in Image process and big data analysis.
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