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Apple Cellular RF Systems Engineering Intern – Phase Lock Loop Austria, Upper Austria, Linz 812039418
18.03.2025
Description
In this role as RFSE PLL intern, you will be part of the best-in-class cellular RFSE Team. You will work closely with transmitter and receiver architecture, RF design and Silicon Validation teams.Your daily work includes the following tasks:Learn PLL and clock architecture basicsWork on real challenges to improve the PLL performance.Help to develop use cases in Python to measure PLL performance and optimize algorithms and settings.Develop scripts in Matlab and Python to evaluate measurement/simulation results.
Minimum Qualifications
- Experience in programming languages (Preferably Python and Matlab)
- You have basic understanding on frequency generation and phase locked loops (PLLs)
- Basic knowledge of mobile communications
- Strong problem solving and social skills.
- Eagerness to learn new things and take up new challenges
- Excellent communication skills, both written & verbal, would be very useful.
- Available for 6 months or more
Preferred Qualifications
- Currently enrolled in a Master Degree program in Electrical Engineering or Physics or Computer Science/engineering or equivalent.
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