OR Bachelor's degree in Computer Science, Computer Engineering, Mathematics, Electrical Engineering, or related field
OR Master's degree in Computer Science, Computer Engineering, Mathematics, Electrical Engineering, or related field
OR PhD degree in Computer Science, Computer Engineering, Mathematics, Electrical Engineering, or related field
Experience in ASIC/FPGA design and/or verification
Other Requirements:
Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to the following specialized security screenings:
Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
Preferred Qualifications:
Ability to deep dive into complex systems architecture, learn from Specification documents, search, find and research relevant resources
Logic and mathematical attitude, ability to understand and analyse complex software algorithms and cope with complexity obstacles
A versatile can-do, problem-solving attitude, deep and thorough, clean and exact results oriented
Ability to work both in a cooperating team and as an individual with self responsibility
Excellent communication skills in English, both written and verbal
Knowledge of Linux environment, experience with developing DA/CAD tools and scripts is an advantage
Responsibilities
Plan and execute Formal Verification proofs for Hardware designs, based on deep understanding of its specification, system architecture, and hardware design and verification principles.
Convert free language specification and architecture documents into Formal Executable Specifications, using System Verilog Assertions (SVA) properties and SystemVerilog environment.
Verify, analyse and debug designs using Formal Verification tools and applications to reach cloud-scale quality and zero critical bugs at production release.
Work with design and verification teams to create multi-discipline verification environment and achieve ultimate possible coverage.
Continuously Improve and develop Formal Verification scripts and functions to improve Formal tools flow, enhance efficiency and coverage
Teach, guide, mentor and support designers and verification engineers using the Formal Verification tools and applications.