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Cisco Sr ASIC design verification engineer 
Taiwan, Taipei, Taipei 
800072386

12.06.2024

You are a talented, motivated ASIC verification engineer to join the team and contribute to the verification of very complex ASICs. You will have a Design Verification background, hands-on experience in System Verilog and UVM methodology, with in-depth knowledge of C++, scripting, as well as ASIC design and verification flow.

You’ll be part of Cisco Common ASIC Group, focusing on developing various test benches and contributing to different aspects of verification infrastructure.

Responsibilities Include:
  • Designing UVM/SystemVerilog testbenches.
  • Defining new DV methodologies.
  • Enhancing existing testbenches.
  • End-to-end verification of various design blocks.
  • Contributing to top level verification.
  • Be a part of emulation testing efforts.
  • Participate in the ASIC bring-up
Education and Experience Required:
  • Bachelor’s or master’s degree in EE and CE.
  • 5-10 years of ASIC Design Verification
Knowledge and Skills:
  • Hands-on and deep understanding of System Verilog and UVM methodology
  • Ability to construct testbench including scoreboard, agents, sequencers, and monitors
  • Ability to debug issues independently
  • Proven Scripting experience (Python, Perl, TCL, shell programming) is a plus
  • Proficient in functional coverage and constrained random DV environments
  • Proficient in merging and analyzing code coverage data generated functional simulation
  • Good written and verbal communication skills
  • Very good hands-on knowledge on latest high speed Ethernet protocol and packets
  • Good working knowledge in C, C++ programming and debugging skills
  • Collaborative and team-focused, with the drive to learn and grow

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