Cisco ASIC Design Verification Engineer/Senior Engineer 

Taiwan, Taipei, Taipei 

280589831

You are a talented, motivated ASIC verification engineer to join the team and contribute to the verification of very complex ASICs. You will have a Design Verification background, hands-on experience in System Verilog and UVM methodology, with in-depth knowledge of C++, scripting, as well as ASIC design and verification flow.

You’ll be part of Cisco Common ASIC Group, focusing on developing various test benches and contributing to different aspects of verification infrastructure.

• Designing UVM/SystemVerilog testbenches.
• Defining new DV methodologies.
• Enhancing existing testbenches.
• End-to-end verification of various design blocks.
• Contributing to top level verification.
• Be a part of emulation testing efforts.
• Participate in the ASIC bring-up

• Bachelor’s or master’s degree in EE and CE.
• Above 3 years of ASIC Design Verification

• Hands-on and deep understanding of System Verilog and UVM methodology
• Ability to construct testbench including scoreboard, agents, sequencers, and monitors
• Ability to debug issues independently
• Proven Scripting experience (Python, Perl, TCL, shell programming) is a plus
• Proficient in functional coverage and constrained random DV environments
• Proficient in merging and analyzing code coverage data generated functional simulation
• Good written and verbal communication skills
• Very good hands-on knowledge on latest high speed Ethernet protocol and packets
• Good working knowledge in C, C++ programming and debugging skills
• Collaborative and team-focused, with the drive to learn and grow

But “Digital Transformation” is an empty buzz phrase without a culture that allows for innovation, creativity, and yes, even failure (if you learn from it.)