המקום בו המומחים והחברות הטובות ביותר נפגשים
Job Area:
Engineering Group, Engineering Group > GPU ASICS Engineering
Responsibilities:
Definition of next generation of GPU power architecture (Compute/Auto/Mobile) requirements for maximizing PPA under high performance constraints - SOC & Chipset Power, Thermal, Reliability & PDN (SOC and System) & System Cost.
Conduct hands-on workload analysis including algorithm optimization and analysis of performance and/or power characterizations to help define our architecture plans.
Carry out and present architectural investigations and studies (including literature and state-of-the-art surveys).
Develop low power/DCVS/voltage/clock/thermal management architectures (HW/FW/SW) including HW accelerators in a micro-controller based management system.
Drive algorithm development for system power minimization with hardware and software collaborators.
Drive roadmap updates through pre-silicon execution phase (verification and emulation) with collaborators.
Ensure productization of power features with firmware and software collaborators.
Collaborate with multiple teams (SOC, Chipset, system PDN, mixed signal IP, product and GPU hardware and software) to ensure continued roadmap updates from gen to gen.
Advance architectural tooling and methodologies.
Invent and file patents on technical solutions to relevant problems
Minimum Qualifications:
Bachelor's degree in Science, Engineering, or related field.
7+ years of power design, power management & power architecture experience.
5+ ASIC design experience.
Strong background in system and hardware design.
Strong background in power methodology, power architecture, clock & reset arch, power management design (core & system) and sensor (analog/digital) usage for high performance and low power.
Strong background in micro-controllers
Design of solutions (HW-SW) & algorithms for execution of power, reliability, voltage (droop and overshoot) and thermal management for highest battery level perf/watt.
Strong understanding of multi clock design concepts.
RTL expertise (Verilog / SystemVerilog).
Ability to work in a team environment.
Expect good self-direction and time management skills.
Preferred Qualifications:
Previous experience with GPU Power Management
Experience with Computer Architecture, C/C++ programming
Verification of low power designs & testplan development
Familiarity with ARM System Architectures (Cortex*, AMBA protocols)
Experience in Embedded System Design
Experience with system debug tools (like T32)
Experience with FW/HW debug utilizing Logic Analyzers, Spectrum Analyzers, Oscilloscope
Experience with: power target definition.
Power and/or performance optimization through simulation & modeling
Minimum Qualifications:
• Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field and 6+ years of Software Engineering, Hardware Engineering, Systems Engineering, or related work experience.
Master's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field and 5+ years of Software Engineering, Hardware Engineering, Systems Engineering, or related work experience.
PhD in Computer Engineering, Computer Science, Electrical Engineering, or related field and 4+ years of Software Engineering, Hardware Engineering, Systems Engineering, or related work experience.
Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.
Pay range:
$216,000.00 - $324,000.00
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