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Google Senior RTL Design Engineer Silicon 
United States, California, Mountain View 
785660270

Yesterday
Minimum qualifications:
  • Bachelor's degree in Electrical Engineering or equivalent practical experience.
  • 8 years of experience with digital logic design principles, RTL design concepts, and languages, such as Verilog or SystemVerilog.
  • Experience with logic synthesis techniques to optimize RTL code, performance and power, as well as low-power design techniques.
  • Experience with a scripting language like Perl or Python.

Preferred qualifications:
  • Master's or PhD degree in Electrical Engineering, Computer Engineering or Computer Science.
  • Experience with ASIC design methodologies for clock domain checks, reset checks and low power design.
  • Knowledge in one of these areas: Processor Cores, Buses/Fabric/NoC, Debug/Trace, Interrupts, Clocks/Reset.
  • Knowledge of FPGA and emulation platforms.
  • Knowledge of ASIC Verification or DFT.