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Microsoft Senior Silicon Design Engineer United States, California, Mountain View 783180009
cutting edgeDesign Engineerto work on leading edgeIP development as part of theustom and Central IP Siliconexcel at
Required Qualifications:
7+ years of related technical engineering experience
o OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience or internship experience
o OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience or internship experience
o OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
- years experiencein digital logic design inSystemVerilog
- years experiencerunning synthesis/staticcheck toolsincludingRTL synthesis, lint, CDC, RDC,and/or
Other Requirements:
to meet Microsoft, customer and/or government security screening requirementsfor this role. These requirements include but are not limited to the following specialized security screenings:
Preferred Qualifications:
11+ years technical engineering experience
o OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience
o OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience
o OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience.
Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:Microsoft will accept applications for the role until January 15, 2025.
Responsibilities
You willbe responsible forleading themicroarchitecture and Register Transfer Level (implementation ofIP blocks, design verification engineersand architects. Individuals will be working ondefining microarchitecture specifications,running static checks,timing analysis. Experience with Verilog/System Verilog
Embody our and
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