What you'll be doing:
Design and maintain the unit level/sub-system Verification environment.
Understand the architecture specifications, develop and carry out the test plan to verify the design.
Create UVM components, sequences, tests and scoreboards.
Sign off on the verification efforts with very high-quality code and functional coverage.
Launch regressions, resolve the issues, and make forward progress towards achieving the DV milestone targets
Automate the manual steps involved in launching build, regression, and triage.
Collaborate with architects, designers, and software engineers to achieve project goals.
Proactively contributes to improving the efficiency of the testbenches by embracing the latest techniques.
Responsible for end-to-end verification of IPs, ensuring the highest quality delivery.
What we need to see:
Bachelor’s or Master’s degree in Computer or Electrical Engineering (or equivalent experience) with 3 years of relevant experience.
Proficient with System Verilog, UVM required and OOPS based programming.
Strong coding skills in Python or other industry-standard scripting languages.
Strong understanding of RTL design (Verilog).
Good understanding of computer architecture fundamentals.
Familiarity with verification tools such as VCS or equivalent simulation tools, and debug tools like Verdi.
You will also be eligible for equity and .
משרות נוספות שיכולות לעניין אותך