Intel Physical Design Engineer 

United States, Texas 

775034159

Who You Are

Responsibilities include but are not limited to:

• Performs physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing.

• Conducts all aspects of the physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis.

• Conducts verification and signoff include formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking.

• Analyzes results and makes recommendations to fix violations for current and future product architecture.

• Possesses expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, placing, routing, synthesis, and DFT using industry standard EDA tools.

• Optimizes design to improve product level parameters such as power, frequency, and area. Participates in the development and improvement of physical design methodologies and flow automation.

Qualifications:

You must possess the minimum education requirements and minimum required qualifications to be initially considered for this position. Relevant experience can be obtained through schoolwork, classes, project work, internships, and/or military experience. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications

• Bachelor's degree in electrical or computer engineering, or a related field with a year of related experience or a master's degree in electrical or computer engineering, or a related field.

• 1+ years of experience with CMOS transistor level circuit fundamentals

• 1+ years of experience with VLSI hardware design and program

3+ years of experience with:

• Design Automation tools, flows and methodology

• Fusion Compiler, Primetime

• Layout cleanup expertise DRCs, density, etc.

• TCL, Python, Perl and/or C++ programming

• TL/Logic design Verilog, VCS, etc.

• Circuit design

• Computer architecture

College GradShift 1 (United States of America)US, California, Santa Clara
Position of Trust

offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US:

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change. The application window for this job posting is expected to end by 04/22/2026