Bachelor’s degree in Electrical Engineering, Computer Engineering, Physics, a related field, or equivalent practical experience.
4 years of experience in Field-programmable Gate Array (FPGA) design and development.
Experience with Register-Transfer Level (RTL) design using Verilog or systemVerilog.
Preferred qualifications:
Master's degree or PhD in Electrical Engineering, Computer Engineering, Physics, or a related field.
Experience with Digital-to-Analog converters (DACs), Analog-to-Digital converters (ADCs), and high-speed communication protocols like Ethernet and PCIe.
Experience with programming languages like C, C++, Python, or scripting languages like TCL.
Experience in FPGA design and verification tools such as Quartus, Vivado, and industry-standard simulation and debugging software.
Ability to Lead FPGA projects or ASIC block development from initial concept to final implementation.
Ability to troubleshoot and resolve intricate design issues in FPGA systems within deployed environments.