Qualcomm Physical Design Engineer 

United States, California, San Diego 

763543324

Job Area:

Engineering Group, Engineering Group > GPU ASICS Engineering

The ideal candidate will have/demonstrate the following:

• Experience in Physical design which includes floor-planning, placement, clock implementation, routing for complex, high frequency designs

• Experience with physical synthesis and implementation tools - Synopsys Fusion Compiler, ICC2 and Cadence Genus/Innovus

• Must have good knowledge of static timing analysis, reliability and power analysis

• Strong understanding of CMOS circuit design and design techniques to push Power, Performance and Area of complex designs

• Ability to think outside the box for innovative solutions to improve power and eliminate performance bottlenecks

• Strong understanding of GPU micro-architecture and collaborate with RTL designers to improve bottlenecks for power and performance

• Solid working knowledge of scripting skills including tcl, perl or python

• Excellent communication skills and collaborating in a team environment is a must

Preferred Skills:

• Clock, power delivery network design, process technology, prior experience in flow and methodology development, block closure

• Hands on experience with Synthesis, DFT, Place and Route, Timing and Reliability Signoff

• Hands on experience working with very complex designs that push the envelope of Power, Performance and Area

• Hands on experience working with sub-micron technology process nodes eg. 5nm, 4nm and below is highly advantageous

• Prior experience in flow and methodology development is an advantage

• RTL expertise (Verilog/System Verilog)

• Excellent debug and analytical skills

• Ability to work well in a collaborative environment with multi-disciplined teams

Minimum Qualifications:

• Bachelor’s degree in Electrical/Computer Engineering

• 3+ years of direct physical design work experience

• Strong background in VLSI design, scripting

• Strong background and experience working with industry standard Synthesis and Place and Route tools including Signoff tools

• Hands on experience taping out designs in sub-micron technology node design < 10nm

• Expect strong self-motivation and time management skills

Preferred Qualifications:

• Master’s degree in Electrical/Computer Engineering

• 6+ years of direct physical design work experience

• In depth end to end experience from RTL2GDS, taping out at least 4 complex designs

Minimum Qualifications:

• Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field and 4+ years of Software Engineering, Hardware Engineering, Systems Engineering, or related work experience.

Master's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field and 3+ years of Software Engineering, Hardware Engineering, Systems Engineering, or related work experience.

PhD in Computer Engineering, Computer Science, Electrical Engineering, or related field and 2+ years of Software Engineering, Hardware Engineering, Systems Engineering, or related work experience.

Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.

Pay range:

$151,000.00 - $227,000.00