Microsoft Senior Engineer - Design Test DFT 

Taiwan, Taoyuan City 

763522122

Required Qualifications:

• Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience
  • OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience
  • OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience
  • OR equivalent experience.
• 4+ years of experience in the field of DFT knowledge about industry standard practice in Design for Test
  • ATPG, JTAG, Memory BIST, and trade-offs between test quality and test time

Other Requirements:

Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to, the following specialized security screenings:

• Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud background check upon hire/transfer and every two years thereafter.

Preferred Qualifications:

• Experience developing Scan architecture & micro-arch specifications as it relates to large SOCs along with scan insertion techniques for IP's like PLL’s, IO’s & Power circuits.
• Expert at Scan ATPG, Stuck-At, At-Speed insertion, boundary coverage, compression & retargeting flows - using EDA tools like Siemens Tessent or Synopsys TestMax.
• Knowledge of Verilog or System Verilog with experience using simulators and waveform debugging tools.
• Ability to pioneer flows for Gate-level simulation (GLS), perform coverage analysis, and debug for achieving high fault coverage.
• Experience with Static Timing Analysis & constraint generation.
• Experience with ATE and Silicon bring-up with proficiency in Mentor Tessent / Synopsys tools for Yield & Diagnosis.
• Proactive & self-motivated, eager to learn and contribute in a team environment, committed and accountable.
• Proficient in scripting languages (Tcl & Perl), and use of AI to improve work efficiency.
• Confident problem solver who thrives under pressure to find new, creative solutions.

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:Microsoft will accept applications for the role until October 22, 2025.

• Own block level DFT arch specification documentation & provide Test solutions (logic & SRAM) for increased coverage, optimal design & lower test time.
• Maintain & enhance existing DFT tools by understanding product needs & tailor solutions for current and upcoming products, also with the use of AI.
• Provide test plans and engage closely with verification engineers to perform waveform reviews.
• Hold a primary role in enabling silicon by working directly with test engineers to bring up test vectors, and analyzing yield & diagnosis.
• Work as part of DFX (Test & Debug) team & closely collaborate with highly energetic cross functional team members (Architects, front-end & back-end design/verification, Physical design, and post-silicon manufacturing) with respect and with One Microsoft mentality to establish synergies.