Microsoft Senior Design Test Engineer 

Taiwan, Taoyuan City 

488501968

Required qualifications:

• Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience
  • OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience
  • OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience
  • OR equivalent experience.
• 2+ years of industry experience as a Design For Test (DFT) engineer.
• Hands on experience with Tessent tools for scan and Memory Built In Self Test (MBIST).
• Hands on experience simulating and debugging Register Transfer Language (RTL) and gate level Design For Test (DFT) features.

Other Requirements:

Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to, the following specialized security screenings:

• Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud background check upon hire/transfer and every two years thereafter.

Preferred qualifications:

• Bachelor’s degree in engineering with 5 years of experience as a DFT engineer or a Master’s degree in engineering with 3 years of experience as a DFT engineer.
• Experience in designing and implementing In System Test structures
• Experience with Synopsys tools for synthesis and STA
• Experience with System Verilog for design and verification
• Post silicon bring up and production vector generation is a plus.
• Knowledge of Perl, Tcl or Python scripting languages

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:Microsoft will accept applications for the role until July 26th, 2025.

• Boundary scan insertion and validation
• MBIST insertion and validation including shared bus MBIST architecture
• EDT, SSN, and logic bist insertion and validation
• ATPG pattern generation and validation for various fault models
• Timing constraint development for DFT structures
• Design and integrate test structures such as fuse, repair and on chip clocking controllers

• Embody our and