Amazon Sr SoC Design – EM/IR Hardware Compute Group 

United States, California, Sunnyvale 

758913739

Work hard. Have fun. Make history.As a EM/IR Lead, Your Roles & Responsibilities:• EM and IR analysis for Power Delivery Network and Standard Cell design.
• Conduct detailed analysis of the PDN at Chip Top and block level to find and address potential IR (Voltage) drop issues for Static IR and Dynamic IR.
• Usage of industry-standard tools and methodologies to perform and analyse power and EM.
• Work with different stakeholders and make necessary convergence for design and power convergence.
• Provide recommendations for layout and design changes to enhance power distribution and minimize IR drop.
• Evaluate the risk of electromigration in the Signal & PDN (power distribution network) and provide necessary recommendations.
• Enhance and automate workflows to improve PDN analysis efficiency.
• Partner with EDA tool vendors to enhance and customize EM/IR analysis tools.
• You will look the IR reports and EM reports and make necessary recommendations to the PnR teams to converge and meet the goals of the design. Role will involve collaboration with Verification teams and get the right vectors for different types of analysis including functional, DFT and other scenarios for which power numbers are needed.

• Bachelor’s degree or higher in EE, CE, or CS
• 10+ years or more of practical semiconductor implementation experience
• Scripting experience with Perl, Python, tcl, shell and drive to automate flows
• Proficiency in chip front-end and back-end implementation tools such as Fusion compiler, Design Compiler, ICC2 or Innovus and Primetime, Tempus
• Must have good communication and analytical skills.
• Should be able to work closely with IP Design teams and Backend Physical Design teams across multiple sites.

• PhD in Computer Science, Electrical Engineering, or related field
• Experience with memory compiler
• Experience with formal equivalence – Cadence Conformal/Synopsys Formality
• Have in depth knowledge of entire design process from Design specification, defining architecture, micro-architecture, RTL design and functional verification
• Experience with DFT and DFM flows