Nvidia Senior Library Design Engineer 

United States, Texas 

751303338

What you'll be doing:

• Characterize standard cell libraries for advanced process technologies

• Develop and support extraction environments for standard cell characterization

• Develop flows to generate standard cell IR and thermal views

• Analyze tradeoffs between different standard cell architectures

• Collaborating with cross functional teams to drive PPA targets and provide guidance

• Analyzing foundry device models & layout dependent effects, collaborate with device group for spice to silicon correlation

• Automate characterization flows, model evaluation and publishing process to improve efficiency

• Validate aging and self-heating effects of device models

What we need to see:

• B.S or M.S. in Electrical Engineering or equivalent experience

• 5+ years industry experience

• An understanding of transistor device behavior, layout dependent device behavior, aging and self-heating effects on advanced FinFET and GAA process nodes

• Strong background in Standard cell design and layout on advanced process nodes

• Hands-on experience with standard cell timing, power, statistical characterization and modeling. Familiar with advanced variation modeling techniques

• Strong experience with gate level spice simulations, variation analysis and parasitic extractions.

• Experience with industry standard layout/schematic editor, physical verification, timing characterization and parasitic extraction tools

• We are looking for someone with excellent programming skills

• Scripting experience with Perl/Python. Layout automation with Cadence Skill is an additional advantage. Familiarity with debugging timing reports

• Great interpersonal skills

• A passion for working closely with foundry partners and providing excellent support for end-users