Marvell Senior Layout Engineer 

Singapore 

742099186

Marvell is the leader of Automotive networking technology development offering a complete portfolio of high-quality AEC-Q100 qualified products and solutions with Ethernet PHY transceivers and switches supporting speeds from 100Mbps to 10Gbps. The enhanced safety and security features, high speed data transfer and process, and co-application processor platforms greatly meet the requirements for today and tomorrow’s in-vehicle networks.
You will join a global ASIC design team, to work in the areas of Digital Design Implementation for Automotive Ethernet Switch and SOC products.

What You Can Expect

• Check RTL design quality; create timing constraints for synthesis and static timing analysis.

• Perform logic synthesis and deliver gate netlist for DFT insertion and physical design.

• Perform timing analysis and timing signoff for chip tapeout.

• Conduct low power design; perform power and IR drop analysis.

• Perform DFT insertion in logic compilation environment.

• Perform formal verification to check logic equivalency between golden and revised design.

• Participate in logic design for timing critical blocks.

• Work closely with and support physical design engineers in Place and Route and design integration.

• Research and evaluate advanced design flows and methodologies for Automotive Ethernet products.

What We're Looking For

• Master’s Degree inElectronics/ElectricalEngineering or related fields with coursework in digital logic design, computer architecture.

• 7~12 years of hand-on experience in digital design, running EDA tools for simulation, synthesis, timing analysis and formal verification.

• Solid knowledge and background in ASIC development.

• Proficiency in Linux shell scripting and scripting languages such as Perl, Python, Tcl, and Make.

• Having passion in technology; being flexible, goal oriented, and team player.

• Excellent verbal and written communication skills.

• RTL coding experience/DFT design experience is a plus.

• Advanced technology and large SOC chip signoff experience is a plus.