Marvell Staff Layout Engineer 

Singapore 

808783421

What You Can Expect

• The position will be responsible for implementing and validation DFT/Test on complex IP and SOC for multiple Custom/Compute ASIC/SoC designs
• The execution involves Implementation of various DFT/DFX features, Scan/MBIST Insertion & Validation, ATPG , IP-DFT, STA, pattern generation & Post-Silicon Bringup and Debug for various designs in Custom/Compute space.
• In this position, the responsibility also includes mentoring, guiding and driving a small team of engineers enabling them for scaling across multiple designs.
• The position also involves definition and enhancement of DFT methodologies and tools to be able to benchmark them and enable new methodologies in the domain of DFT/Test.

What We're Looking For

• Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 10+ years of related professional experience.
• Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 8+ years of experience.
• Hands on working experience in various stages of DFT-Execution SCANInsertion/ATPG/MBIST/Validation/STA/IP-DFX/Post-SiliconBringup/Debug
• Strong fundamentals in Digital Circuit Design and Logic Design is required
• Knowledge on various DFT/Test solutions
• Understanding of DFT Flows and Methodologies and Experience withSiemens/Synopsys/CadenceTool set(Tessent/DC,Spyglass,Tmax,VCS/Genus,Modus,NCSim)
• Prior experience in ASIC design is a plus
• Scripting skills using PERL, Tcl and C-Shell is plus