You will collaborate closely with Senior FPGA Engineers, Systems Architects, and other cross-functional teams on complex projects that require creative problem-solving and a deep understanding of FPGA development. This role not only offers technical challenges but also provides opportunities to advance your skills in cutting-edge networking and hardware design.
Key Responsibilities:
- Design and implement advanced FPGA modules, including RTL coding and logic partitioning, using System Verilog.
- Develop verification plans and self-checking simulation test environments to verify system functionality and ensure design robustness, using System Verilog / UVM-based verification environments.
- Contribute to architectural decisions, develop module micro-architectures, and ensure designs operate seamlessly with other modules in the system.
- Debug and validate FPGA designs in lab environments using tools such as oscilloscopes, logic analyzers, and traffic generators like IXIA, in a Python based lab test infrastructure.
- Analyze design data and lab results to validate expected performance metrics, guide optimizations, and produce thorough documentation.
- Drive innovation in high-speed interfaces (e.g., PCIe, Ethernet MACs, AXI) and memory structures.
- Mentor and provide technical guidance to junior engineers to enhance team capabilities.
- Collaborate with cross-functional teams to deliver reliable and high-quality products.
We’re looking for innovators with strong technical skills, excellent problem-solving abilities, and a keen interest in driving high-performance designs.
Minimum Qualifications:
- Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related technical field.
- 4–6 years of industry experience in FPGA development, including RTL coding in System Verilog.
- Ability to approach complex issues with creativity, adapting industry best practices to F5’s unique challenges.
- Excellent verbal and written communication skills, with the ability to collaborate across teams.
Preferred Skills and Experience:
- Ethernet networking fundamentals.
- Knowledge of high-speed FPGA interfaces such as PCIe, Ethernet MACs, GCI, and AXI.
- Familiarity with memory architectures and interfaces.
- Experience working with lab tools like bus analyzers, oscilloscopes, and logic analyzers.
- Exposure to traffic generation tools (e.g., IXIA) for testing and validation.
- Familiarity with design repositories such as GitLab and Perforce.
- Ability to apply Ai tools such as GitLab Duo, GitHub Copilot, and ChatGPT to improve design development efficiency.
- A proactive attitude with a strong problem-solving mindset.
This position follows a hybrid work model. While you'll primarily work from our Spokane office, we offer flexibility for partial remote work. Additionally, occasional travel—approximately 5%—may be required for project needs.
What You’ll Love About F5:
- Make an Impact: Contribute to cutting-edge technology that powers global digital transformations.
- Collaborative Culture: Work with brilliant minds in a diverse, welcoming, and supportive environment.
- Career Growth: Unlock opportunities for professional development, mentorship, and leadership.
- Flexible Work Arrangements: Balance your work and life with our supportive hybrid model.
- Comprehensive Benefits: Enjoy competitive pay and robust health, wellness, and retirement plans.
The Job Description is intended to be a general representation of the responsibilities and requirements of the job. However, the description may not be all-inclusive, and responsibilities and requirements are subject to change.
The annual base pay for this position is: $124,800.00 - $187,200.00