Nvidia Senior Physical Design Full Chip STA Engineer 

Israel, North District 

740386078

Perform advanced Static Timing Analysis (STA) for NiC and SoC projects.

Running Prime Time, review and debug timing paths, understand constraints, sdc generation, timing ecos generation.

Identify convergence risks and work closely with physical design, RTL and DFT teams, ensuring convergence throughout various project stages.

Responsible for a full timing closer and quality approval from pre-layout STA model through signoff.

B.SC./ M.SC. in Electrical Engineering.

At least 6+ years of hands-on STA experience.

Experience in Prime Time and signoff methodologies.

Excellent leadership capabilities.

Knowledge in physical design flows and methodologies (Synthesis, PNR, DFT designs).

Trong background of Prime time tool.

Great teammate.