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Nvidia Full Chip STA Engineer 
Israel, Tel Aviv District, Tel Aviv-Yafo 
387501983

31.07.2024

What you will be doing:

  • Be in charge of full chip level STA convergence from early stages to signoff.

  • Take part in Full Chip floor plan design and Netlist creation with aim to optimize timing convergence and work efficiency.

  • Define and optimize, together with CAD, STA signoff flows and methodologies.

  • Digital Partitions' and analog IPs' timing integration, giving feedback and driving convergence.

  • Work closely with logic design and DFT engineers to define and implement constraints for the various work modes, including optimizing them for runtime and efficiency.

What we need to see:

  • B.SC./ M.SC. in Electrical Engineering/Computer Engineering.

  • 3+ years of experience in physical design and STA

  • Proven experience in RTL2GDS and STA flows and methodologies.

  • Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.) and timing signoff (Primetime).

  • Great teammate.