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Mobileye Formal Verification Engineer 
Israel, Haifa District, Haifa 
731439173

04.05.2025
What will your job look like:
  • Be the owner of formal verification environment from first draft to sign-off stage
  • Apply formal methods to verify the correctness of various complex digital systems
  • Work with HW architects\designers to define assumptions, rules and cover properties
  • Help define the formal verification methodology and environment to be applied by the team
  • Explore new Formal methods and Tools
  • Work with tools like Cadence JasperGold, Verisium manager, Xcelium, Indago
  • Analyze verification results, identify bugs, and collaborate with engineers to resolve design issues
  • Develop generic formal blocks\functions of commonly used logic, to be later used off the shelf
All you need is:
  • BSc in electrical engineering, computer engineering, or computer science
  • Passion for the field of Formal Verification
  • 3+ years of experience in Formal Verification
  • Understanding and mastering hardware description languages (HDLs) like Verilog/SystemVerilog and programming languages such as Python or C++
  • Strong analytical and problem solving skills
  • Ability to work independently and in a team-oriented environment
  • Participating in last semester Formal Verification course in the Technion - advantage.