Nvidia Senior Mask Design Engineer 

United States, Texas 

731097547

What you will be doing:

• Perform physical

  layout
  of SRAM and datapath circuits using
  Cadence
  tools.

• Your duties will include floor-planning, hierarchical

  layout
  assembly, effective use of cell sharing and custom
  layout
  of pitch related cell design.

• Ability to recognize different solutions in

  layout
  implementation based on area, metal utilization and schedule.

• Participate in developing physical verification flows for new technologies - DRC and LVS

• Work closely with circuit engineers to help to establish

  layout
  design methodologies to enable an efficient and expeditious
  layout
  implementation.

What we need to see:

• Bachelor’s Degree or equivalent experience

• 5+ years' proven experience in memory macro

  layout

• Strong background in tight pitch related

  layout
  design

• Knowledge of the latest FinFET technology nodes and design rules

• Strong proficiency of

  layout
  tools (
  Cadence
  Virtuoso
  is desired)

• Knowledge of ICV

  layout
  verification tool is a plus

• Scripting skills in CSH, PERL or SKILL

• Excellent interpersonal skills and ability to work with multi-functional teams

• Excellent writing and reporting skills