Qualcomm Sr Physical Synthesis Implementation Engineer 

United States, California, San Diego 

718505190

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

Principal Duties & Responsibilities

• Implement Hierarchical blocks of the DDR/system cache subsystem running the physical synthesis with Synopsys Fusion Compiler.

• Work with RTL designers on managing complex power intent

• Manage timing constraints

• Trouble shoot upf issues in synthesis

• Run Conformal Low Power Checks on final netlist and resolve clp violations

• Run Power Aware Conformal Logic Equilalency Check: both RTL 2 Gate and Gate 2 Gate.

• Run STA on final netlist and support PD timing/congestion closure

• Work with RTL designers and PDteamin evaluateing and executing both manual and tool generated (Conformal eco) functional eco

Skills

• Working independently with little supervision.

• Using verbal and written communication skills to convey complex and/or detailed information to multiple individuals/audiences with differing knowledge levels. May require strong negotiation and influence, communication to large groups or high-level constituents.

• Completing tasks that require multiple steps that can be performed in various orders; tasks require simultaneously executing multiple cognitive abilities and maintaining information in short- or long-term memory.

• Using deductive and inductive problem solving; multiple approaches may be taken/necessary to solve the problem; often information is missing or conflicting; advanced data analysis and interpretation skills are required.

Required Competencies (All competencies below are required upon entry)

• Analytical Skills - The ability to collect information and identify fundamental patterns/trends in data. This includes the ability to gather, integrate, and interpret information from several sources.

• Communication - The ability to convey information clearly and accurately, as well as choosing the most effective method of delivery (e.g., email, phone, face-to-face). This includes using a technically sound communication style both verbally and in writing.

• Getting Work Done - The ability to be organized, resourceful, and planful. This includes the ability to leverage multiple resources to get things done and lay out tasks in sufficient detail. This also includes the ability to get things done with fewer resources and in less time, work on multiple tasks at once without losing track, and foresee and plan around obstacles.

• Proficient in running Physical synthesis with Synopsys Fusion Compiler on SoC Top Level blocks with complex power intent.

• Proficient running Cadence Conformal Low Power checks on block with complex power intent.

• Proficient in running Cadence Conformal Power Aware Logic Equivalency Checks.

• Proficient in running STA with Synopsys PTSI.

Qualifications

• Bachelor's degree in Engineering.

• 5+ years Hardware Engineering experience or related work experience.

Preferred Qualifications

• Bachelor/Master's Degree in Engineering

• 8+ years Hardware Engineering experience or related work experience.

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.

Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.

PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.

Pay range:

$140,000.00 - $210,000.00