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Google Circuits Design Engineer Clock University United States, California, Sunnyvale 715630541
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Minimum qualifications:
Preferred qualifications:
- PhD degree in Electrical Engineering or equivalent practical experience.
- Experience in clock architecture and designing high speed clock distribution circuits.
- Experience in Spice simulations, clock verification, and signoff.
Preferred qualifications:
- Experience in ASIC physical design, physical design flows, and methodologies including synthesis, place and route, Static Timing Analysis (STA), formal verification, Change Data Capture (CDC), and power analysis.
- Experience in IP integration (e.g., Phase Lock Loops (PLLs), memories, and Analog IP) and analog routing.
- Experience in a scripting language (e.g., Python, Perl or TCL).
- Knowledge of Verilog/System Verilog.
- Familiarity with low power design techniques (e.g., multi Vth/power/voltage domain design, clock gating, power gating, Dynamic Voltage Frequency Scaling (DVFS)/AVS, etc.).
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