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Google RTL Design Engineer Security 
India, Karnataka, Bengaluru 
708220091

22.07.2024
Minimum qualifications:
  • 5 years of experience in designing RTL digital logic using System Verilog for FPGA/Application-Specific Integrated Circuit (ASIC).
  • Experience in scripting language such as Perl or Python.
  • Experience in area, power and performance optimization.

Preferred qualifications:
  • Master's degree or PhD in Electrical Engineering, Computer Science, or equivalent practical experience.
  • Experience in design and development of security blocks or crypto blocks.