Intel DFT Design Engineer 

United States, Texas 

703555420

Job Description:

• Develops the logic design, register transfer level (RTL) coding, simulation, and providesDFTtiming closure support as well as test content generation and delivery to manufacturing for various DFx content (including SCAN, MBIST, and BSCAN).

• Participates and collaborates in the definition of architecture and microarchitecture features of the block, subsystem, and SoC underDFTbeing designed (including TAP, SCAN, MBIST, BSCAN, proc monitors, in system test/BIST).

• Develops HVM content for rapid bring up and ramp to production on the automatic test equipment (ATE). Applies various strategies, tools, and methods to write and generate RTL and structural code to integrateDFT.

• Optimizes logic to qualify the design to meet power, performance, area, timing, test coverage, DPM, and test time/vectormemory reductiongoals as well as design integrity for physical implementation. Reviews the verification plan and drives verification of theDFTdesign to achieve desired architecture and microarchitecturespecifications.

• Ensures design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. IntegratesDFTblocks into functional IP and SoC and supports SoC customers to ensure high quality integration of the IP block.

• Collaborates with post silicon and manufacturing team to verify the feature on silicon, support debug requirements, and document all learnings and improvements requirement in design and validation.

• Drives high test coverage through structural and specific IP tests to achieve the quality and DPM objectives of the product and develops HVM content for rapid bring up and production on the ATE.

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Experience would be obtained through a combination of prior education level classes, and current level school classes, projects, research, and relevant previous job and/or internship

Minimum Qualifications:

• Bachelor's degree in electrical engineering, computer science or related field with 4+ years of industry experience OR

• Master's degree in Electrical Engineering, computer science or related field with 3+ years of industry experience

Technical Experience:

• 5+ years of experience with DFT

• 1+ years of experience with Synopsys or Cadence tools

Preferred Qualifications:

• Expertise in Tessent DFT tool

• Primetime expertise, especially in DFT constraints

Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and orschoolwork/classes/research.

Experienced HireShift 1 (United States of America)US, California, Santa Clara, US, Massachusetts, Hudson, US, Oregon, Hillsboro, US, Texas, Austin
Position of Trust

Weoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US:

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change. The application window for this job posting is expected to end by 03/21/2025