Master's degree in Electrical Engineering, Computer Engineering, Physics, a related field, or equivalent practical experience.
6 years of experience working in a signal integrity technical environment, or 5 years of experience with an advanced degree.
3 years of experience in technical leadership.
Preferred qualifications:
PhD in Electrical Engineering, Computer Engineering, Physics, a related field, or equivalent practical experience.
Experience with Allegro, HFSS, SIwave, ADS, Matlab, PowerDC, PowerSI.
Experience with the product development process for mass volume production design, with a focus on signal integrity, power integrity and lab validation.
Lab experience with SerDes testing. Understanding of SERDES capabilities.
Scripting experience for data collection and analysis (e.g., Python, bash). Understanding of FEC and its implications for system design.
Familiarity with PCIE, DDR, SATA, Ethernet standards, PCB, connector, and/or cable design and assembly processes, including materials and component selection.