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Google Physical Design Engineer Static Timing Analysis United States, California, Sunnyvale 678858664
24.06.2024
Minimum qualifications:
Preferred qualifications:
- Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.
- 5 years of experience in static timing (i.e., to create full chip timing constraints, perform full chip static timing analysis and timing ECO creation).
- Experience in working across various physical design areas (i.e., EDA scripting, block level synthesis, floorplanning, place and route, and congestion mitigating utilizing standard EDA tools).
- Experience in full chip timing sign-off checklist criteria and overseeing final timing sign-off for ASICs.
Preferred qualifications:
- 12 years of experience in the domain of physical design and static timing analysis.
- Experience leading one or more aspects of physical design or physical design flow/methodology, to successful tape-outs and shipping silicon.
- Experience in full chip design planning and working with multiple foundries.
- Experience in extraction of design parameters, QoR metrics, and analyzing data trends.
- Knowledge of semiconductor device physics and transistor characteristics.
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