Microsoft Hardware Verification Engineer 

United States, California, Mountain View 

668410959

Required Qualifications:

• 5+ years of related technical engineering experience
  • OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 2+ years technical engineering experience or internship experience
  • OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience or internship experience.
• 3+ years of experience in developing test plans, creating simulation environments, developing tests, and debugging for multiple IPs, SoCs or systems.
• Technical experience in coding languages including, but not limited, to in Verilog or VHDL, C/C++, Python, Ruby or Perl.

Other Requirements:

Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings:

Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud background check upon hire/transfer and every two years thereafter.

Preferred Qualifications:

• 8+ years technical engineering experience
  • OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience
  • OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience
  • OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:Microsoft will accept applications for the role until February 10, 2025.

• Plan the verification of complex design IP interacting with the architecture and design engineers to identify verification test scenarios.
• Create and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify designs with SVA and industry leading formal tools
• Develop tests using UVM or C/C++
• Analyse and debug test failures with designers to deliver functionally correct design.
• Identify and write functional coverage for stimulus and corner cases.
• Close coverage to plug verification holes and meet tape out requirements.
• Other
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