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Google SOC Design Engineer 
United States, California, Sunnyvale 
668097235

17.06.2024
Minimum qualifications:
  • Bachelor's degree in Electrical Engineering or equivalent practical experience.
  • 2 years of experience in ASIC design flows and methodologies, with 1 year of experience in IP integration (e.g., subsystems, memories, IO's and Analog IP) and RTL design.
  • Experience in scripting languages (e.g., Python, Tcl, or Perl) and with Verilog/System Verilog.
  • Experience working on various technologies (e.g., embedded processors, DDR, SerDes, networking-on-chip fabrics, etc.).

Preferred qualifications:
  • Experience with ASIC design methodologies for clock domain checks, reset checks and low power design.
  • Experience with silicon, emulation, FPGA validation and debug, functional verification, physical design, and DFT methodologies.
  • Experience with SOC implementation standards and interfaces.
  • Experience with low power design techniques, power gating, multi-voltage designs.
  • Experience with industry standard integration tools.
  • Experience on recent technology nodes.