Qualcomm PDK/CAD Engineer - Physical Verification Extraction Development 

India, Karnataka, Bengaluru 

664965882

Job Area:

Engineering Group, Engineering Group > Hardware Engineering

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.

Minimum Qualifications:

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.

Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

Job Overview

In this highly cross functional role, you will be part of the Global Design Enablement team responsible for the physical verification aspects of PDK development. You will conceptualize, develop, maintain and improve the Physical Verification flows. The role requires you to work on flow and rule deck development for various technology nodes utilizing the state of the art tools. You will be collaborating with the Custom Digital/Analog/Mixed Signal/RF, Physical design (PD) and Chip integration teams to understand their requirements and challenges and enabling flows to meets their needs. This role requires a thorough understanding of Design Rule Checks (DRC), Layout Versus Schematic (LVS) and Layout and Programmable ERC, implementing the rules from scratch and/or modify the existing ones

Minimum Qualification

Minimum 5 years’ experience in a hands-on PDK role

Experience with developing and customization of the Fill and DFM flows

As a member of the Physical Verification CAD team, you will maintain and improve all aspects of physical verification flow and methodology

You will need to have a deep understanding of design rule checks (DRC) and layout versus schematic (LVS) runsets, writing from scratch and/or modify existing ones.

Proficiency in integration and tech setup of Calibre LVS with StarRC/QRC and other Extraction tools

Understanding of Digital/Custom/Analog requirements for various post layout electrical flows

Knowledge of deep sub-micron FINFET, Planar, SOI and PMIC process technologies and mask layout design

Proficiency in one or more of the programming/scripting languages – SKILL, Python, Unix, Perl and TCL.

Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.