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As a member of our Memory Subsystem Design team, you will collaborate with architects, software engineers, and circuit designers to and deliver a world-class solution. NVIDIA Memory controllers are among the industry's most complex because of the many protocols that are supported and the stringent requirements of our high end graphics controllers and SOCs.
In this position, you will have the opportunity to be responsible for the micro-architecture and design including RTL design, synthesis, functional verification and timing analysis using groundbreaking CAD tools and using the latest process technologies.
BS or equivalent experience in Electrical Engineering or Computer Engineer or related degree required, advanced degrees (MS, PhD) a plus.
5+ years of meaningful industry experience and a background in high speed DRAM and/or processor design (ie Graphics, Microprocessors, Network Processors, or Mobile / Multimedia SOCs).
Knowledge ofHBM, GDDR, LPDDR, or DDRor related protocols.
You have experience with all stages in the ASIC design flow including emulation, prototyping, DFT, timing analysis, floor planning, ECO, bringup & lab debug, and ATE test development.
Strong working knowledge of Verilog or VHDL.
Experience with high speed clocking, cache interfaces and protocols.
Familiarity with board and system level issues.
Programming skills in C and/or PERL.
Good communication skills and interpersonal skills are required. A history of mentoring junior engineers and interns a huge plus.
You will also be eligible for equity and .
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