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Apple PHY RTL Design Engineer United States, California, Irvine 656209423
03.04.2025
Develop signal processing intensive design for wireless communication SoCs, including: - Writing specifications, other documents and defining Microarchitecture based on MATLAB/C system model - Architecting area and power efficient low latency designs with scalabilities, and flexibilities - Work with algorithm and software team to ensure performance, and power efficiency - Power and Area efficient RTL logic design, and DV support - Running tools to ensure lint and CDC/RDC clean design - Synthesis and timing constraints - Experience in design of signal processing Wireless protocols
- BS and 3+ years of relevant industry experience
- Ideally at least 3 years of industry experience in wireless PHY design engineering
- Strong fixed-point knowledge and extensive experience with bit-true cycle-accurate verifications
- Understanding of Decoders - Viterbi, LDPC, Polar
- Understanding of Filter design, multi-radix implementation, and compromises
- Knowledgeable in modern design techniques and energy-efficient/low-power logic design, and power analysis
- Familiarity with power estimation (vector-less and vector-based), modeling, profiling, and post-silicon power correlation
- Solid understanding of wireless standards, such as IEEE 802.11, 802.15, Bluetooth, or 3GPP is a plus
- Background in computer architecture
- Bus fabric, especially APB/AHB/AXI
- Power management with multiple power domains
- Proven track record of bringing logic designs into high-volume production
- Ability to work well in a team and be productive under ambitious schedules
- Should exhibit excellent interpersonal skills and be self-motivated and well-organized
- Experience with FPGA and/or emulation platform desired
- Excellent communication skills – both written and oral
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
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