מציאת משרת הייטק בחברות הטובות ביותר מעולם לא הייתה קלה יותר
Apple Cellular SOC Design Verification Engineer United States, Texas, Austin 653675795
16.05.2024
Key Qualifications
- Dedicated/hands-on ASIC DV experience.
- Advanced knowledge of HVL methodology (UVM/OVM) with most recent experience in UVM.
- Proven record of working full ASIC cycle from concept to tape-out to bring-up.
- Experience taping out large SOC systems with embedded processor cores.
- Hands-on verification experience of PCIe, Bus Fabric, NOC, AHB, AXI, based bus architecture in UVM environment.
- In-depth knowledge and experience working with low-power design, UPF integration, boot-up, power cycling, and HW/FW interaction verification.
- Should be a great teammate with excellent communication and problem-solving skills and the desire to seek diverse challenges.
- BS and a minimum of 3 years of relevant industry experience is required.
Description
Understand details of High-Efficiency SOC Architecture, standard SOC peripherals such as SPI, I2C, UART, Timer, DMA, memory management schemes, low power spec, multi-processor systems, DDR, PCIe, DDR, Memory Controller Sub Systems, USB, PLL, power up, Secured Boot schemes.Build coverage-driven verification plans from specifications, and review and refine them to achieve coverage targets.Create IP level module and sub-system verification plan, TB, portable test benches, sequences, and test infrastructure.Architect UVM-based highly reusable test benches and integrate sophisticated multi-instance VIPs, sub-system test benches, and test suites to SOC level, achieve targeted coverage, and work with design, architecture, SW, FW, and external IP delivery teams to efficiently integrate and verify overall SOC design.Work closely with DV methodology architects to improve verification flow.
Education & Experience
BS and a minimum of 3 years of relevant industry experience is required.MSEE or beyond is preferred.
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