Intel DTCO APR Engineer 

Malaysia, Penang 

641959763

Job Description:

Join Intel and seize the opportunity to innovate and expand computing technology, connecting and enriching the lives of every person on Earth. As a DTCO (Design Technology Co-Optimization) engineer, you will engage in all aspects of the SoC design flow, from high-level design to synthesis, place and route, timing, and power, to create optimal designs.As a DTCO APR engineer, your responsibilities will include, but are not limited to:

• Supporting RTL synthesis and conducting place and route experiments using both internal and external vendor tools to enhance Intel's product Power, Performance, and Area (PPA) for current and future process nodes on internal Intel Architecture (IA/X86) and external ARM IPs.
• Managing changes in floorplan, corresponding scaling, and assessing their impact on power, congestion, and timing for the current technology node, while predicting their effects on power, routing, and timing scaling for the next technology node.
• Improving cell utilization and transistor density metrics by leveraging cutting-edge tools and methodologies.
• Analyzing power (dynamic and leakage), performance (setup and hold), enhancing critical path timing, reducing congestion by optimizing the use of available metal layers, debugging tools, and more.

Qualifications:

• Bachelor's Degree (Master's Degree preferred) in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• 5+ years of relevant experience in silicon design and/or TFM development.

Experience in the following areas:

• Proficiency in at least one of the following: Python, Perl, TCL, Shell scripting.
• Use of industry-standard placement and routing CAD tools.
• Proven track record in Si Tape Out.

Preferred Qualifications:

• Experience in floor planning and power grid setup, clock methodologies, IR droop and SI mitigation strategies, power and timing signoff conditions, and leveraging industry-standard tools, flows, and methodologies to achieve optimal PPA tradeoffs.
• Experience in feasibility studies or technology pathfinding.
• Experience in more than one ASIC Digital Implementation TFM ( SNPS / CDNS / Others ).
• Background in Artificial Intelligence and Machine Learning (AI-ML).

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