Samsung Design Technology Co-Optimization DTCO Engineer flow Methodology 

United States, Texas, Austin 

606630599

Role and Responsibilities

As a highly experienced DTCO engineer, you will help propel Samsung SARC/ACL’s innovation forward by building highly efficient design and analysis flows and methodologies for DTCO. With strong expertise in digital design flows spanning synthesis, PnR, EM/IR, STA, PV and large-design space exploration, you will drive collaboration with the IP development teams to ensure process technology, design rule, standard cell design and design methodology changes are consumable throughout the product development cycle to meet or exceed product key performance indicators.

• You are an innovator. You are skilled at developing CAD flows for custom design with a mindset to continuously push the PPA(power/performance/area)envelope on aggressive designs with a high level of automation for DTCO needs.

• You have a curious mindset and thrive on navigating the unknown through innovation and continuous learning. You will explore a methodology to achieve low-power and high-performance goals for Samsung-specific SOC design styles.

• You have expertise in one or many technical areas, including concepts of logic/physical synthesis, automated place and route, power estimation, and standard cell design.

• You are a problem solver. You enjoy solving CAD and design methodology-related challenges and creating analysis methodologies and metrics most relevant to removing bottlenecks for improvement.

• You thrive in a production and result-oriented environment, working on high-impact, large-scale projects that have a global impact.

• You are skilled at working effectively with various stakeholders by using clear and precise communication skills for technical requirements and specifications, while proactively driving collaboration with cross-functional teams.

• You are detail oriented. You can provide and maintain thorough documentation, publish results, and fulfill other project management-related needs.

• You are a self-starter and driver. You enjoy seeking new problems and owning solutions to drive toward production.

Skills and Qualifications

• 15+ years of experience with a Bachelor’s Degree in Computer Science/Engineering, or 13+ years of experience with a Master’s Degree, or 11+ years of experience with a Ph.D.

• 10+ years of custom design tools and methodology development experience.

• 10+ years of experience with industry standard automated design tools for synthesis, place and route, EM/IR analysis, static timing analysis and/or physical verification.

• 10+ years of experience working with Cadence Innovus and/or Synopsys Fusion Compiler and reference flows.

• Experience with PPA analysis across standard cell library, memory compiler, interconnect stack options and block-level PPA evaluation.

• Strong knowledge of CMOS fundamentals, device physics, device-technology interactions, scaling trends, and design and implementation challenges at advanced technology nodes.

• Experience working with batch run oriented environments for design space exploration and high throughput.

• Experience working with foundries is a plus.

• Experience in improving productivity, efficiency and/or quality of results through machine-learning (ML) practices is preferred.

• Strong skills withscripting/programminglanguages like Tcl, Perl, Python.

• Strong data analysis skills to analyze and deduce information from large data sets and apply the learnings to other scenarios.

U.S. Export Control

This position requires the ability to access information subject to U.S. export control restrictions. Applicants must have the ability to access export-controlled information or be eligible to receive a government authorization to access export-controlled information.