Master's degree in Computer Science, Electrical Engineering, a related field, or equivalent practical experience.
3 years of experience in technical circuit and physical design field.
Experience in transistor level design in advanced finfet technology nodes (i.e. SPICE simulations or concurrent optimization across custom circuit/IP and physical design spaces.
Preferred qualifications:
Experience delivering optimized custom circuits/memories/IPs and digital blocks leading to product tapeout.
Experience with programming/scripting (Python, TCL).
Understanding of characterization and verification of standard cells/SRAMs/register files, including knowledge of power, noise, variation, and IR analysis.
Understanding of design kit collaterals for front end and back end design teams.
Familiarity with industry standard tools for synthesis, place and route, and static timing analysis.