מציאת משרת הייטק בחברות הטובות ביותר מעולם לא הייתה קלה יותר
Google ASIC Engineer IP Design Silicon United States, California, Mountain View 639673929
Yesterday
Minimum qualifications:
Preferred qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 5 years of experience with RTL design using Verilog/System Verilog and microarchitecture.
- Experience with a scripting language like Python or Perl.
- Experience with ARM-based SoCs, interconnects and ASIC methodology.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- 8 years of industry experience with IP design.
- Experience with methodologies for low power estimation, timing closure, synthesis.
- Experience with methodologies for RTL quality checks (e.g., Lint, CDC, RDC).
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