

What You’ll Be Doing
Develop comprehensive test plans and implement them using formal verification tools.
Create assertions, assumptions, and cover properties to validate design behavior.
Employ abstraction techniques to manage complexity and achieve verification goals.
Analyze and debug failures in the RTL design.
Collaborate with architecture, design, and verification teams to communicate coverage and ensure design quality.
What we need to see:
BS/MS/PhD in CS, CE, EE, or Mathematics (or equivalent experience)with 3+ years relevant experience
Strong problem-solving skills and the ability to thrive in a collaborative, distributed team environment.
Proficiency in scripting languages like TCL, Python, or Perl.
Ways to stand out from the crowd:
Hands-on experience with formal verification tools such as JasperGold or VC Formal.
Experience with formal verification methodologies, SystemVerilog, and temporal logic.
משרות נוספות שיכולות לעניין אותך