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Apple RTL Design Engineer United States, North Carolina, Cary 631676038
07.04.2025
Are you early in your journey towards a chip design career and wish to challenge yourself in a technical and multi-disciplinary effort, we have an exciting position for you in the world class Apple mixed-signal silicon design team. This position will encourage building of a solid foundation in logic circuits and entry into understanding analog circuits. You will gain a deeper understanding into a variety of flows fundamental to modern silicon engineering: insight into full custom schematics for analog as well as high-speed digital circuits, translating functionality of such circuits into an efficient software behavioral representation, simulation of such code and ensuring formal equivalence between custom designs and their abstract representation. You will gain experience and knowledge into software methods and analysis that is increasingly important for a variety of disciplines.
In this job you will get the opportunity to gain knowledge in designing micro-architecting digital blocks within sophisticated mixed-signal circuits with embedded micro-controller, advanced DFT architectures and very low power design requirements. You will be also responsible for RTL coding of blocks specified by you or others. You will participate in the design verification and bring-up of such blocks by writing RTL assertions, debugging code, and otherwise interacting with the design verification team. Additionally, you will support and validate various front end methodology flows that include pre-silicon power analysis, clock domain crossing, reset domain crossing and unified power flow (UPF). You will also participate in the lab bring-up of those circuits by potentially writing test scripts, analyzing lab data, proposing experiments, etc.
- BS degree in technical discipline with minimum 3 years of proven experience.
- Solid understanding of mixed signal concepts, RTL design, Verilog and SystemVerilog.
- Good fundamental knowledge of front-end tools and methodologies (Verilog simulators, linters, clock-domain crossing, reset domain crossing, unified power flow, logic equivalence checkers).
- Validated knowledge of synthesis, static timing, DFT, is a plus.
- Validated knowledge of SystemVerilog assertions, checkers, and other design verification techniques are a plus.
- Knowledge of scripting languages. Perl and Python are plusses.
- Strong communication and presentation skills.
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