Synthesis, Physical design and implementation of CPU cores, system interconnect and other ARM Designs.
Analyze design timing, area and power to help improve the quality of ARM Design.
Optimize design, flow and methodologies to achieve best in class PPAT working with various internal and external teams.
Develop and deploy new methodologies to improve implementation efficiency and results
Support and develop detailed implementation analysis and data-mining methodologies.
Work with implementation and physical IP RTL design teams to drive analysis and optimization of our IP.
Converting R&D concepts into real implementation solutions.
Enable our partners to achieve the best possible quality of results
Required Skills and Experience :
Bachelors or Master’s degree equivalent in Electrical Engineering, Computer Engineering or other relevant technical fields.
7+ years of proven experience in ASIC Implementation, Physical design, STA and Timing closure, Structured clock tree, PDN analysis, DFM and Physical verification
Strong Communication and Problem Solving Skills.
Experience in crafting and adopting new silicon implementation techniques and methodologies and promote their use with international teams
Experience working closely in top and block level Synthesis, Floor planning, Place and Route, CTS, logical and physical optimization, timing closure and power analysis flows.
Proven programming and scripting skills eg. Tcl, Perl, Python, Make.
“Nice To Have” Skills and Experience :
Knowledge around Arm based SoCs!
Experience with low power design techniques (power gating, voltage/frequency scaling)
Experience with Verilog RTL design.
Experience with ATPG tools/and or production testing.